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cpu.hpp
1#ifndef CPU_HPP
2#define CPU_HPP
3
4#include <stdint.h>
5#include <map>
6#include <string>
7#include <queue>
8
9class Bus;
10
16{
17 uint32_t ins;
18
24
30 Instruction(uint32_t ins) : ins(ins) {}
31
37 uint32_t opcode() { return ins >> 26; }
38
44 uint32_t rs() { return (ins >> 21) & 0x1f; }
45
51 uint32_t rt() { return (ins >> 16) & 0x1f; }
52
58 uint32_t rd() { return (ins >> 11) & 0x1f; }
59
66 uint32_t shamt() { return (ins >> 6) & 0x1f; }
67
74 uint32_t funct() { return ins & 0x3f; }
75
81 uint32_t imm() { return ins & 0xffff; } // Bits 15-0
82
88 uint32_t addr() { return ins & 0x3ffffff; } // Bits 25-0
89};
90
96{
101 uint32_t reg;
102
107 uint32_t data;
108
113 uint32_t delay;
114
120
127 RegisterLoad(uint32_t reg, uint32_t data): reg(reg), data(data) { delay = 0; }
128
136 RegisterLoad(uint32_t reg, uint32_t data, uint32_t delay): reg(reg), data(data), delay(delay) {}
137};
138
144class CPU
145{
146public:
147 CPU();
148
155 void connectBus(Bus* bus) { this->bus = bus; }
156
157 void clock();
158
159private:
160 void load_next_ins();
161 void decode_and_execute();
162
163 uint32_t read32(uint32_t addr);
164 void write32(uint32_t addr, uint32_t data);
165 uint16_t read16(uint32_t addr);
166 void write16(uint32_t addr, uint16_t data);
167 uint8_t read8(uint32_t addr);
168 void write8(uint32_t addr, uint8_t data);
169
170private:
176
182 std::queue<RegisterLoad> load_queue;
183
188 uint32_t pc = 0;
189
194 uint32_t ir;
195
200 uint32_t ir_next;
201
207
212 uint32_t regs[32] = {0xdeaddeed};
213
219 uint32_t hi = 0;
220
226 uint32_t lo = 0;
227
233 uint32_t cop0_status;
234
240 uint32_t cop0_bpc;
241
247 uint32_t cop0_bda;
248
254 uint32_t cop0_dcic;
255
261 uint32_t cop0_bdam;
262
267 uint32_t cop0_bpcm;
268
274 uint32_t cop0_cause;
275
276private:
277 void branch(uint32_t offset);
278 void set_reg(uint8_t reg, uint32_t data);
279 uint32_t get_reg(uint8_t reg);
280 void load_regs();
281 void conf_ins_lookup();
283
284public:
285 void show_regs();
286 void reset();
287
288private:
293 std::map<uint8_t, void (CPU::*)()> lookup_op;
294
299 std::map<uint8_t, void (CPU::*)()> lookup_special;
300
305 std::map<uint8_t, void (CPU::*)()> lookup_cop0;
306
311 std::map<uint8_t, void (CPU::*)()> lookup_cop2;
312
317 std::map<uint8_t, std::string> lookup_mnemonic_op;
318
323 std::map<uint8_t, std::string> lookup_mnemonic_special;
324
325 void LUI();
326 void ORI();
327 void SW();
328 void ADDIU();
329 void J();
330 void BNE();
331 void ADDI();
332 void LW();
333 void SH();
334 void JAL();
335 void ANDI();
336 void SB();
337 void LB();
338 void BEQ();
339 void BGTZ();
340 void BLEZ();
341 void LBU();
342 void SLTI();
343 void SLTIU();
344
345 void SPECIAL();
346 void SLL();
347 void OR();
348 void SLTU();
349 void ADDU();
350 void JR();
351 void AND();
352 void ADD();
353 void JALR();
354 void SRA();
355 void SUBU();
356 void DIV();
357 void MFLO();
358 void SRL();
359 void DIVU();
360 void MFHI();
361 void SLT();
362
363 void BLGE();
364 void BLTZ();
365 void BGEZ();
366 void BGEZAL();
367 void BLTZAL();
368
369 void COP0();
370 void MTC0();
371 void MFC0();
372
373 void COP1();
374
375 void COP2();
376
377 void COP3();
378};
379
380#endif
Class to implement the Bus.
Definition bus.hpp:78
Class to emulate the CPU.
Definition cpu.hpp:145
std::map< uint8_t, std::string > lookup_mnemonic_op
Lookup table for the mnemonics of instructions.
Definition cpu.hpp:317
uint8_t read8(uint32_t addr)
Read a 8 bit word from the bus.
Definition cpu_rw.cpp:69
void COP1()
Looks up and executes the appropriate coprocessor 1 instruction. (UNUSED)
Definition cpu.cpp:46
void SLTIU()
Set on Less Than Immediate Unsigned.
Definition ins.cpp:581
void BEQ()
Branch on Equal.
Definition ins.cpp:329
void write16(uint32_t addr, uint16_t data)
Write a 16 bit word to the bus.
Definition cpu_rw.cpp:55
void BLGE()
Choose between BLTZAL, BGEZAL, BLTZ, BGEZ.
Definition ins.cpp:427
void clock()
Clocks the CPU once.
Definition cpu.cpp:33
std::map< uint8_t, void(CPU::*)()> lookup_op
Lookup table for instructions.
Definition cpu.hpp:293
void JR()
Jump Register.
void JAL()
Jump and Link.
Definition ins.cpp:228
uint32_t read32(uint32_t addr)
Read a 32 bit word from the bus.
Definition cpu_rw.cpp:13
void SLTU()
Set on Less Than Unsigned.
void LUI()
Load Upper Immediate.
Definition ins.cpp:13
std::map< uint8_t, void(CPU::*)()> lookup_cop0
Lookup table for cop0 instructions (opcode = 0b010000)
Definition cpu.hpp:305
void OR()
Bitwise OR.
void SRA()
Shift Right Arithmetic.
void DIV()
Divide.
void MFHI()
Move From HI.
CPU()
Construct a new CPU object.
Definition cpu.cpp:16
void COP2()
Looks up and executes the appropriate coprocessor 2 (Graphics) instruction.
Definition ins_cop2.cpp:7
void ADD()
Add.
void SUBU()
Subtract Unsigned.
uint32_t hi
HI register.
Definition cpu.hpp:219
Bus * bus
Pointer to the Bus object.
Definition cpu.hpp:175
std::map< uint8_t, std::string > lookup_mnemonic_special
Lookup table for the mnemonics of special instructions.
Definition cpu.hpp:323
uint32_t cop0_bdam
Bitmask applied to COP0 breakpoint exception register (data)
Definition cpu.hpp:261
uint32_t cop0_bpc
COP0 breakpoint exception register.
Definition cpu.hpp:240
void conf_mnemonic_lookup()
Configures the mnemonic lookup table. (for debugging)
Definition cpu_conf.cpp:90
void BLEZ()
Branch on Less Than or Equal to Zero.
Definition ins.cpp:377
void load_next_ins()
Load the next instruction into the instruction register.
Definition cpu_utils.cpp:10
void branch(uint32_t offset)
Branches to the given offset.
Definition cpu_utils.cpp:44
uint32_t ir
Instruction register.
Definition cpu.hpp:194
void MFLO()
Move From LO.
void BGEZAL()
Branch on Greater Than or Equal to Zero And Link.
Definition ins.cpp:531
void SLL()
Shift Left Logical.
void SLTI()
Set on Less Than Immediate.
Definition ins.cpp:559
void reset()
Resets the CPU to its initial state.
Definition cpu_conf.cpp:9
void MFC0()
Move From Coprocessor 0.
Definition ins_cop0.cpp:90
void conf_ins_lookup()
Configures the instruction lookup table.
Definition cpu_conf.cpp:36
uint32_t ir_next
Instruction immediately after the current instruction in the memory.
Definition cpu.hpp:200
void SLT()
Set on Less Than.
void connectBus(Bus *bus)
Connects Bus to the CPU.
Definition cpu.hpp:155
void SRL()
Shift Right Logical.
std::map< uint8_t, void(CPU::*)()> lookup_special
Lookup table for special instructions (opcode = 0b000000)
Definition cpu.hpp:299
void LBU()
Load Byte Unsigned.
Definition ins.cpp:405
void J()
Unconditional Jump.
Definition ins.cpp:94
Instruction ins
Instruction in the form of the Instruction structure.
Definition cpu.hpp:206
uint32_t cop0_status
COP0 status register.
Definition cpu.hpp:233
void load_regs()
Loads the registers from the load queue.
Definition cpu_utils.cpp:85
void JALR()
Jump and Link Register.
void write8(uint32_t addr, uint8_t data)
Write a 8 bit word to the bus.
Definition cpu_rw.cpp:83
void write32(uint32_t addr, uint32_t data)
Write a 32 bit word to the bus.
Definition cpu_rw.cpp:27
uint32_t regs[32]
General purpose registers.
Definition cpu.hpp:212
uint32_t cop0_dcic
COP0 breakpoint exception register (hardware)
Definition cpu.hpp:254
void DIVU()
Divide Unsigned.
uint32_t cop0_bda
COP0 breakpoint exception register (data)
Definition cpu.hpp:247
void ORI()
Bitwise OR Immediate.
Definition ins.cpp:27
void BLTZAL()
Branch on Less Than Zero And Link.
Definition ins.cpp:481
void LB()
Load Byte.
Definition ins.cpp:301
uint32_t pc
Program counter.
Definition cpu.hpp:188
void ADDIU()
Add Immediate Unsigned.
Definition ins.cpp:75
void show_regs()
Shows the values of the registers.
void AND()
Bitwise AND.
void BNE()
Branch on Not Equal.
Definition ins.cpp:109
void SW()
Store Word.
Definition ins.cpp:45
void ADDU()
Add Unsigned.
void LW()
Load Word.
Definition ins.cpp:173
std::map< uint8_t, void(CPU::*)()> lookup_cop2
Lookup table for cop1 instructions (opcode = 0b010001)
Definition cpu.hpp:311
void decode_and_execute()
Decodes and executes the instruction in the instruction register.
Definition cpu_utils.cpp:25
void ADDI()
Add Immediate.
Definition ins.cpp:137
uint32_t cop0_cause
COP0 cause register.
Definition cpu.hpp:274
void set_reg(uint8_t reg, uint32_t data)
Sets the value of the given register from the general purpose registers.
Definition cpu_utils.cpp:61
uint32_t get_reg(uint8_t reg)
Gets the value of the given register from the general purpose registers.
Definition cpu_utils.cpp:74
void BGEZ()
Branch on Greater Than or Equal to Zero.
Definition ins.cpp:508
void SPECIAL()
Looks up and executes the appropriate SPECIAL instruction.
void BLTZ()
Branch on Less Than Zero.
Definition ins.cpp:458
void ANDI()
Bitwise AND Immediate.
Definition ins.cpp:248
void SH()
Store Halfword.
Definition ins.cpp:199
void COP0()
Looks up and executes the appropriate coprocessor 1 instruction.
Definition ins_cop0.cpp:10
void COP3()
Looks up and executes the appropriate coprocessor 3 instruction. (UNUSED)
Definition cpu.cpp:55
uint16_t read16(uint32_t addr)
Read a 16 bit word from the bus.
Definition cpu_rw.cpp:41
std::queue< RegisterLoad > load_queue
Queue to store the loads to the general purpose registers.
Definition cpu.hpp:182
void MTC0()
Move to Coprocessor 0.
Definition ins_cop0.cpp:37
void SB()
Store Byte.
Definition ins.cpp:268
uint32_t lo
LO register.
Definition cpu.hpp:226
void BGTZ()
Branch on Greater Than Zero.
Definition ins.cpp:353
uint32_t cop0_bpcm
Bitmask applied on COP0 breakpoint exception register.
Definition cpu.hpp:267
Structure to access different parts of an instruction by value.
Definition cpu.hpp:16
uint32_t opcode()
Opcode of the instruction. Size: 6 bits [31-26].
Definition cpu.hpp:37
uint32_t imm()
Immediate value for the instruction. Size: 16 bits [15-0].
Definition cpu.hpp:81
uint32_t rt()
Target register for the instruction. Size: 5 bits [20-16].
Definition cpu.hpp:51
uint32_t addr()
Address value for jump/branch instructions. Size: 26 bits [25-0].
Definition cpu.hpp:88
uint32_t rd()
Destination register for the instruction. Size: 5 bits [15-11].
Definition cpu.hpp:58
uint32_t funct()
Function field for the instruction. Size: 6 bits [5-0].
Definition cpu.hpp:74
uint32_t rs()
Source register for the instruction. Size: 5 bits [25-21].
Definition cpu.hpp:44
Instruction(uint32_t ins)
Construct a new Instruction object.
Definition cpu.hpp:30
Instruction()
Construct a new Instruction object.
Definition cpu.hpp:23
uint32_t shamt()
Shift amount for the instruction. Size: 5 bits [10-6].
Definition cpu.hpp:66
Struture to store details of loads to the general purpose registers.
Definition cpu.hpp:96
RegisterLoad(uint32_t reg, uint32_t data, uint32_t delay)
Construct a new RegisterLoad object with delay.
Definition cpu.hpp:136
RegisterLoad(uint32_t reg, uint32_t data)
Construct a new RegisterLoad object with no delay.
Definition cpu.hpp:127
uint32_t delay
Delay in clock cycles.
Definition cpu.hpp:113
RegisterLoad()
Construct a new RegisterLoad object.
Definition cpu.hpp:119
uint32_t reg
Register ID.
Definition cpu.hpp:101
uint32_t data
Data to be loaded.
Definition cpu.hpp:107