cpu_utils.cpp

#include <iostream>
#include <sstream>
#include <core/cpu/cpu.hpp>
 
void CPU::load_next_ins()
{
    ir = ir_next;
    ir_next = read32(pc);
    ins = Instruction(ir);
    pc += 4;
}
 
void CPU::decode_and_execute()
{
    if(lookup_op.find(ins.opcode()) != lookup_op.end())
    {
        (this->*lookup_op[ins.opcode()])();
        return;
    }
    //throw unhandled instruction error
    std::stringstream ss;
    ss << "Unhandled instruction: " << std::hex << ir;
    throw std::runtime_error(ss.str());
}
 
void CPU::branch(uint32_t offset)
{
    pc -= 4; //undo pc increment to point to next instruction
    uint32_t multiplied = offset << 2;
    if((multiplied & 0x80000000) != (offset & 0x80000000))
    {
        std::cout << "MISTAKE!";
    }
    pc += multiplied;
}
 
void CPU::set_reg(uint8_t reg, uint32_t data)
{
    // gpreg_out[reg] = data;
    // gpreg_out[0] = 0; // $zero register
    load_queue.push(RegisterLoad(reg, data));
}
 
uint32_t CPU::get_reg(uint8_t reg)
{
    // return gpreg_in[reg];
    return regs[reg];
}
 
void CPU::load_regs()
{
    uint8_t num_loads = load_queue.size();
    for(int i = 0; i < num_loads; i++)
    {
        RegisterLoad load = load_queue.front();
        load_queue.pop();
        load.delay--;
        if(load.delay == 0xffffffff)
            regs[load.reg] = load.data;
        else
            load_queue.push(load);
    }
    regs[0] = 0; // $zero register
}
 
void CPU::show_regs()
{
    std::cout << "Registers:\n";
    for(int i = 0; i < 32; i++)
    {
        std::cout << "R" << i << ": " << std::hex << regs[i] << "\t";
        if(i % 4 == 3)
            std::cout << "\n";
    }
    std::cout << "HI: " << std::hex << hi << "\tLO: " << std::hex << lo << "\n";
 
}