WolPSX
Loading...
Searching...
No Matches
cpu_conf.cpp
1#include "core/cpu/cpu.hpp"
2
9void CPU::reset()
10{
11 regs[0] = 0;
12 for(int i = 1; i < 32; i++)
13 regs[i] = 0xdeadbeef;
14 hi = 0xdeadbeef;
15 lo = 0xdeadbeef;
16
17 pc = 0xbfc00000;
18
19 cop0_bda = 0x00000000;
20 cop0_bpcm = 0x00000000;
21 cop0_bpc = 0x00000000;
22 cop0_dcic = 0x00000000;
23 cop0_bdam = 0x00000000;
24 cop0_status = 0x00000000;
25 cop0_cause = 0x00000000;
26
27 ins = Instruction(0x00000000);
28 ir = 0x00000000;
29 ir_next = 0x00000000;
30}
31
36void CPU::conf_ins_lookup()
37{
38 lookup_op[0b000000] = &CPU::SPECIAL;
39 lookup_op[0b010000] = &CPU::COP0;
40 lookup_op[0b010001] = &CPU::COP1;
41 lookup_op[0b010010] = &CPU::COP2;
42 lookup_op[0b010011] = &CPU::COP3;
43
44 lookup_op[0b001111] = &CPU::LUI;
45 lookup_op[0b001101] = &CPU::ORI;
46 lookup_op[0b101011] = &CPU::SW;
47 lookup_op[0b001001] = &CPU::ADDIU;
48 lookup_op[0b000010] = &CPU::J;
49 lookup_op[0b000101] = &CPU::BNE;
50 lookup_op[0b001000] = &CPU::ADDI;
51 lookup_op[0b100011] = &CPU::LW;
52 lookup_op[0b101001] = &CPU::SH;
53 lookup_op[0b000011] = &CPU::JAL;
54 lookup_op[0b001100] = &CPU::ANDI;
55 lookup_op[0b101000] = &CPU::SB;
56 lookup_op[0b100000] = &CPU::LB;
57 lookup_op[0b000100] = &CPU::BEQ;
58 lookup_op[0b000111] = &CPU::BGTZ;
59 lookup_op[0b000110] = &CPU::BLEZ;
60 lookup_op[0b100100] = &CPU::LBU;
61 lookup_op[0b000001] = &CPU::BLGE;
62 lookup_op[0b001010] = &CPU::SLTI;
63 lookup_op[0b001011] = &CPU::SLTIU;
64
65 lookup_special[0b000000] = &CPU::SLL;
66 lookup_special[0b100101] = &CPU::OR;
67 lookup_special[0b101011] = &CPU::SLTU;
68 lookup_special[0b100001] = &CPU::ADDU;
69 lookup_special[0b001000] = &CPU::JR;
70 lookup_special[0b100100] = &CPU::AND;
71 lookup_special[0b100000] = &CPU::ADD;
72 lookup_special[0b001001] = &CPU::JALR;
73 lookup_special[0b000011] = &CPU::SRA;
74 lookup_special[0b100011] = &CPU::SUBU;
75 lookup_special[0b011010] = &CPU::DIV;
76 lookup_special[0b010010] = &CPU::MFLO;
77 lookup_special[0b000010] = &CPU::SRL;
78 lookup_special[0b011011] = &CPU::DIVU;
79 lookup_special[0b010000] = &CPU::MFHI;
80 lookup_special[0b101010] = &CPU::SLT;
81
82 lookup_cop0[0b00100] = &CPU::MTC0;
83 lookup_cop0[0b00000] = &CPU::MFC0;
84}
85
90void CPU::conf_mnemonic_lookup()
91{
92 lookup_mnemonic_op[0b000000] = "SPECIAL";
93 lookup_mnemonic_op[0b010000] = "COP0";
94 lookup_mnemonic_op[0b010001] = "COP1";
95 lookup_mnemonic_op[0b010010] = "COP2";
96 lookup_mnemonic_op[0b010011] = "COP3";
97 lookup_mnemonic_op[0b001111] = "LUI";
98 lookup_mnemonic_op[0b001101] = "ORI";
99 lookup_mnemonic_op[0b101011] = "SW";
100 lookup_mnemonic_op[0b001001] = "ADDIU";
101 lookup_mnemonic_op[0b000010] = "J";
102 lookup_mnemonic_op[0b000101] = "BNE";
103 lookup_mnemonic_op[0b001000] = "ADDI";
104 lookup_mnemonic_op[0b100011] = "LW";
105 lookup_mnemonic_op[0b101001] = "SH";
106 lookup_mnemonic_op[0b000011] = "JAL";
107 lookup_mnemonic_op[0b001100] = "ANDI";
108 lookup_mnemonic_op[0b101000] = "SB";
109 lookup_mnemonic_op[0b100000] = "LB";
110 lookup_mnemonic_op[0b000100] = "BEQ";
111 lookup_mnemonic_op[0b000111] = "BGTZ";
112 lookup_mnemonic_op[0b000110] = "BLEZ";
113 lookup_mnemonic_op[0b100100] = "LBU";
114 lookup_mnemonic_op[0b000001] = "BLGE";
115 lookup_mnemonic_op[0b001010] = "SLTI";
116 lookup_mnemonic_op[0b001011] = "SLTIU";
117
118 lookup_mnemonic_special[0b000000] = "SLL";
119 lookup_mnemonic_special[0b000000] = "SLL";
120 lookup_mnemonic_special[0b100101] = "OR";
121 lookup_mnemonic_special[0b101011] = "SLTU";
122 lookup_mnemonic_special[0b100001] = "ADDU";
123 lookup_mnemonic_special[0b001000] = "JR";
124 lookup_mnemonic_special[0b100100] = "AND";
125 lookup_mnemonic_special[0b100000] = "ADD";
126 lookup_mnemonic_special[0b001001] = "JALR";
127 lookup_mnemonic_special[0b000011] = "SRA";
128 lookup_mnemonic_special[0b100011] = "SUBU";
129 lookup_mnemonic_special[0b011010] = "DIV";
130 lookup_mnemonic_special[0b010010] = "MFLO";
131 lookup_mnemonic_special[0b000010] = "SRL";
132 lookup_mnemonic_special[0b011011] = "DIVU";
133 lookup_mnemonic_special[0b010000] = "MFHI";
134 lookup_mnemonic_special[0b101010] = "SLT";
135}
CPU::lookup_mnemonic_op
std::map< uint8_t, std::string > lookup_mnemonic_op
Lookup table for the mnemonics of instructions.
Definition cpu.hpp:317
CPU::COP1
void COP1()
Looks up and executes the appropriate coprocessor 1 instruction. (UNUSED)
Definition cpu.cpp:46
CPU::SLTIU
void SLTIU()
Set on Less Than Immediate Unsigned.
Definition ins.cpp:581
CPU::BEQ
void BEQ()
Branch on Equal.
Definition ins.cpp:329
CPU::BLGE
void BLGE()
Choose between BLTZAL, BGEZAL, BLTZ, BGEZ.
Definition ins.cpp:427
CPU::lookup_op
std::map< uint8_t, void(CPU::*)()> lookup_op
Lookup table for instructions.
Definition cpu.hpp:293
CPU::JR
void JR()
Jump Register.
Definition ins_special.cpp:92
CPU::JAL
void JAL()
Jump and Link.
Definition ins.cpp:228
CPU::SLTU
void SLTU()
Set on Less Than Unsigned.
Definition ins_special.cpp:63
CPU::LUI
void LUI()
Load Upper Immediate.
Definition ins.cpp:13
CPU::lookup_cop0
std::map< uint8_t, void(CPU::*)()> lookup_cop0
Lookup table for cop0 instructions (opcode = 0b010000)
Definition cpu.hpp:305
CPU::OR
void OR()
Bitwise OR.
Definition ins_special.cpp:47
CPU::SRA
void SRA()
Shift Right Arithmetic.
Definition ins_special.cpp:178
CPU::DIV
void DIV()
Divide.
Definition ins_special.cpp:220
CPU::MFHI
void MFHI()
Move From HI.
Definition ins_special.cpp:326
CPU::COP2
void COP2()
Looks up and executes the appropriate coprocessor 2 (Graphics) instruction.
Definition ins_cop2.cpp:7
CPU::ADD
void ADD()
Add.
Definition ins_special.cpp:130
CPU::SUBU
void SUBU()
Subtract Unsigned.
Definition ins_special.cpp:202
CPU::hi
uint32_t hi
HI register.
Definition cpu.hpp:219
CPU::lookup_mnemonic_special
std::map< uint8_t, std::string > lookup_mnemonic_special
Lookup table for the mnemonics of special instructions.
Definition cpu.hpp:323
CPU::cop0_bdam
uint32_t cop0_bdam
Bitmask applied to COP0 breakpoint exception register (data)
Definition cpu.hpp:261
CPU::cop0_bpc
uint32_t cop0_bpc
COP0 breakpoint exception register.
Definition cpu.hpp:240
CPU::conf_mnemonic_lookup
void conf_mnemonic_lookup()
Configures the mnemonic lookup table. (for debugging)
Definition cpu_conf.cpp:90
CPU::BLEZ
void BLEZ()
Branch on Less Than or Equal to Zero.
Definition ins.cpp:377
CPU::ir
uint32_t ir
Instruction register.
Definition cpu.hpp:194
CPU::MFLO
void MFLO()
Move From LO.
Definition ins_special.cpp:262
CPU::SLL
void SLL()
Shift Left Logical.
Definition ins_special.cpp:32
CPU::SLTI
void SLTI()
Set on Less Than Immediate.
Definition ins.cpp:559
CPU::reset
void reset()
Resets the CPU to its initial state.
Definition cpu_conf.cpp:9
CPU::MFC0
void MFC0()
Move From Coprocessor 0.
Definition ins_cop0.cpp:90
CPU::conf_ins_lookup
void conf_ins_lookup()
Configures the instruction lookup table.
Definition cpu_conf.cpp:36
CPU::ir_next
uint32_t ir_next
Instruction immediately after the current instruction in the memory.
Definition cpu.hpp:200
CPU::SLT
void SLT()
Set on Less Than.
Definition ins_special.cpp:342
CPU::SRL
void SRL()
Shift Right Logical.
Definition ins_special.cpp:277
CPU::lookup_special
std::map< uint8_t, void(CPU::*)()> lookup_special
Lookup table for special instructions (opcode = 0b000000)
Definition cpu.hpp:299
CPU::LBU
void LBU()
Load Byte Unsigned.
Definition ins.cpp:405
CPU::J
void J()
Unconditional Jump.
Definition ins.cpp:94
CPU::ins
Instruction ins
Instruction in the form of the Instruction structure.
Definition cpu.hpp:206
CPU::cop0_status
uint32_t cop0_status
COP0 status register.
Definition cpu.hpp:233
CPU::JALR
void JALR()
Jump and Link Register.
Definition ins_special.cpp:160
CPU::regs
uint32_t regs[32]
General purpose registers.
Definition cpu.hpp:212
CPU::cop0_dcic
uint32_t cop0_dcic
COP0 breakpoint exception register (hardware)
Definition cpu.hpp:254
CPU::DIVU
void DIVU()
Divide Unsigned.
Definition ins_special.cpp:296
CPU::cop0_bda
uint32_t cop0_bda
COP0 breakpoint exception register (data)
Definition cpu.hpp:247
CPU::ORI
void ORI()
Bitwise OR Immediate.
Definition ins.cpp:27
CPU::LB
void LB()
Load Byte.
Definition ins.cpp:301
CPU::pc
uint32_t pc
Program counter.
Definition cpu.hpp:188
CPU::ADDIU
void ADDIU()
Add Immediate Unsigned.
Definition ins.cpp:75
CPU::AND
void AND()
Bitwise AND.
Definition ins_special.cpp:109
CPU::BNE
void BNE()
Branch on Not Equal.
Definition ins.cpp:109
CPU::SW
void SW()
Store Word.
Definition ins.cpp:45
CPU::ADDU
void ADDU()
Add Unsigned.
Definition ins_special.cpp:79
CPU::LW
void LW()
Load Word.
Definition ins.cpp:173
CPU::ADDI
void ADDI()
Add Immediate.
Definition ins.cpp:137
CPU::cop0_cause
uint32_t cop0_cause
COP0 cause register.
Definition cpu.hpp:274
CPU::SPECIAL
void SPECIAL()
Looks up and executes the appropriate SPECIAL instruction.
Definition ins_special.cpp:10
CPU::ANDI
void ANDI()
Bitwise AND Immediate.
Definition ins.cpp:248
CPU::SH
void SH()
Store Halfword.
Definition ins.cpp:199
CPU::COP0
void COP0()
Looks up and executes the appropriate coprocessor 1 instruction.
Definition ins_cop0.cpp:10
CPU::COP3
void COP3()
Looks up and executes the appropriate coprocessor 3 instruction. (UNUSED)
Definition cpu.cpp:55
CPU::MTC0
void MTC0()
Move to Coprocessor 0.
Definition ins_cop0.cpp:37
CPU::SB
void SB()
Store Byte.
Definition ins.cpp:268
CPU::lo
uint32_t lo
LO register.
Definition cpu.hpp:226
CPU::BGTZ
void BGTZ()
Branch on Greater Than Zero.
Definition ins.cpp:353
CPU::cop0_bpcm
uint32_t cop0_bpcm
Bitmask applied on COP0 breakpoint exception register.
Definition cpu.hpp:267
Instruction
Structure to access different parts of an instruction by value.
Definition cpu.hpp:16
Generated by doxygen 1.10.0