1#include <core/cpu/cpu.hpp>
19 ss <<
"Unhandled instruction (COP0): " << std::hex <<
ir;
20 throw std::runtime_error(ss.str());
54 ss <<
"Unhandled nonzero write to COP0 register (MTC0): " <<
ins.
rd();
55 throw std::runtime_error(ss.str());
64 ss <<
"Unhandled nonzero write to COP0 CAUSE register (MTC0): " <<
ins.
rd();
65 throw std::runtime_error(ss.str());
71 ss <<
"Unhandled COP0 register (MTC0): " <<
ins.
rd();
72 throw std::runtime_error(ss.str());
101 std::stringstream ss;
102 ss <<
"Unhandled COP0 register (MFC0): " <<
ins.
rd();
103 throw std::runtime_error(ss.str());
std::map< uint8_t, void(CPU::*)()> lookup_cop0
Lookup table for cop0 instructions (opcode = 0b010000)
uint32_t ir
Instruction register.
void MFC0()
Move From Coprocessor 0.
Instruction ins
Instruction in the form of the Instruction structure.
uint32_t cop0_status
COP0 status register.
uint32_t get_reg(uint8_t reg)
Gets the value of the given register from the general purpose registers.
void COP0()
Looks up and executes the appropriate coprocessor 1 instruction.
std::queue< RegisterLoad > load_queue
Queue to store the loads to the general purpose registers.
void MTC0()
Move to Coprocessor 0.
uint32_t rt()
Target register for the instruction. Size: 5 bits [20-16].
uint32_t rd()
Destination register for the instruction. Size: 5 bits [15-11].
uint32_t rs()
Source register for the instruction. Size: 5 bits [25-21].
Struture to store details of loads to the general purpose registers.