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ins_cop0.cpp
1#include <core/cpu/cpu.hpp>
2#include <sstream>
3#include <iostream>
4
11{
12 if(lookup_cop0.find(ins.rs()) != lookup_cop0.end())
13 {
14 (this->*lookup_cop0[ins.rs()])();
15 return;
16 }
17 //throw unhandled instruction error
18 std::stringstream ss;
19 ss << "Unhandled instruction (COP0): " << std::hex << ir;
20 throw std::runtime_error(ss.str());
21}
22
38{
39 switch(ins.rd())
40 {
41 case 12:
43 break;
44 case 3:
45 case 5:
46 case 6:
47 case 7:
48 case 9:
49 case 11:
50 //Throw runtime error if value other than 0 is written
51 if(get_reg(ins.rt()) != 0)
52 {
53 std::stringstream ss;
54 ss << "Unhandled nonzero write to COP0 register (MTC0): " << ins.rd();
55 throw std::runtime_error(ss.str());
56 }
57 break;
58 case 13:
59 // cop0_cause = get_reg(ins.rt());
60 //if nonzero value written, throw error
61 if(get_reg(ins.rt()) != 0)
62 {
63 std::stringstream ss;
64 ss << "Unhandled nonzero write to COP0 CAUSE register (MTC0): " << ins.rd();
65 throw std::runtime_error(ss.str());
66 }
67 break;
68 default:
69 //throw unhandled instruction error
70 std::stringstream ss;
71 ss << "Unhandled COP0 register (MTC0): " << ins.rd();
72 throw std::runtime_error(ss.str());
73 }
74}
75
91{
92 switch(ins.rd())
93 {
94 case 12: //Status
96 break;
97 case 13: //Cause
98 break;
99 default:
100 //throw unhandled instruction error
101 std::stringstream ss;
102 ss << "Unhandled COP0 register (MFC0): " << ins.rd();
103 throw std::runtime_error(ss.str());
104 }
105}
std::map< uint8_t, void(CPU::*)()> lookup_cop0
Lookup table for cop0 instructions (opcode = 0b010000)
Definition cpu.hpp:305
uint32_t ir
Instruction register.
Definition cpu.hpp:194
void MFC0()
Move From Coprocessor 0.
Definition ins_cop0.cpp:90
Instruction ins
Instruction in the form of the Instruction structure.
Definition cpu.hpp:206
uint32_t cop0_status
COP0 status register.
Definition cpu.hpp:233
uint32_t get_reg(uint8_t reg)
Gets the value of the given register from the general purpose registers.
Definition cpu_utils.cpp:74
void COP0()
Looks up and executes the appropriate coprocessor 1 instruction.
Definition ins_cop0.cpp:10
std::queue< RegisterLoad > load_queue
Queue to store the loads to the general purpose registers.
Definition cpu.hpp:182
void MTC0()
Move to Coprocessor 0.
Definition ins_cop0.cpp:37
uint32_t rt()
Target register for the instruction. Size: 5 bits [20-16].
Definition cpu.hpp:51
uint32_t rd()
Destination register for the instruction. Size: 5 bits [15-11].
Definition cpu.hpp:58
uint32_t rs()
Source register for the instruction. Size: 5 bits [25-21].
Definition cpu.hpp:44
Struture to store details of loads to the general purpose registers.
Definition cpu.hpp:96