ins.cpp

#include <core/cpu/cpu.hpp>
#include <iostream>
#include <sstream>
 
void CPU::LUI()
{
    set_reg(ins.rt(), ins.imm() << 16);
}
 
void CPU::ORI() //Bitwise OR Immediate
{
    set_reg(ins.rt(), get_reg(ins.rs()) | ins.imm());
}
 
void CPU::SW()
{
    //if cache is isolated
    if(cop0_status & 0x00010000)
    {
        //TODO: Implement Cache
        std::cout << "Ignoring SW as cache is isolated.\n";
        return;
    }
 
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    write32(get_reg(ins.rs()) + offset, get_reg(ins.rt()));
}
 
void CPU::ADDIU()
{
    uint32_t data_se = ins.imm();
    //pad offset with bit at 16th position
    if(data_se & 0x8000)
    {
        data_se |= 0xffff0000;
    }
    set_reg(ins.rt(), get_reg(ins.rs()) + data_se);
 
    // std::cout << "Added " << std::hex << data_se << " to " << get_reg(ins.rs()) << " to get " << get_reg(ins.rt()) << "\n"; //REMOVE
}
 
void CPU::J()
{
    pc = ((pc - 4) & 0xf0000000) | (ins.addr() << 2);
}
 
void CPU::BNE()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    if(get_reg(ins.rs()) != get_reg(ins.rt()))
    {
        branch(offset);
    }
}
 
void CPU::ADDI()
{
    uint32_t extended_imm = ins.imm();
    //pad offset with bit at 16th position
    if(extended_imm & 0x8000)
    {
        extended_imm |= 0xffff0000;
    }
    //check for signed overflow
    //TODO: Handle signed overflow exception
    if(((extended_imm & 0x80000000) && (get_reg(ins.rs()) & 0x80000000) && (((get_reg(ins.rs()) + extended_imm) & 0x80000000) == 0))
        || (((extended_imm & 0x80000000) == 0) && ((get_reg(ins.rs()) & 0x80000000) == 0) && ((get_reg(ins.rs()) + extended_imm) & 0x80000000)))
    {
        //throw signed overflow error
        std::stringstream ss;
        ss << "Signed overflow in ADDI: " << std::hex << ir;
        throw std::runtime_error(ss.str());
    }
 
    set_reg(ins.rt(), get_reg(ins.rs()) + extended_imm);
}
 
void CPU::LW()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
 
    load_queue.push(RegisterLoad(ins.rt(), read32(get_reg(ins.rs()) + offset), 1));
}
 
void CPU::SH()
{
    //if cache is isolated
    if(cop0_status & 0x00010000)
    {
        //TODO: Implement Cache
        std::cout << "Ignoring SH as cache is isolated.\n";
        return;
    }
 
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    write16(get_reg(ins.rs()) + offset, get_reg(ins.rt()) & 0xffff);
}
 
void CPU::JAL()
{
    // std::cout << "Jumped to: " << std::hex << ((pc & 0xf0000000) | (ins.addr() << 2)) << "\n"; //REMOVE
    // uint32_t ra = pc + 4;
    uint32_t ra = pc;
    pc = ((pc - 4) & 0xf0000000) | (ins.addr() << 2);
    set_reg(31, ra);
}
 
void CPU::ANDI()
{
    uint32_t data = ins.imm() & get_reg(ins.rs());
    set_reg(ins.rt(), data);
}
 
void CPU::SB()
{
    //if cache is isolated
    if(cop0_status & 0x00010000)
    {
        //TODO: Implement Cache
        std::cout << "Ignoring SB as cache is isolated.\n";
        return;
    }
 
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    write8(get_reg(ins.rs()) + offset, get_reg(ins.rt()) & 0xff);
}
 
void CPU::LB()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    uint32_t data_s = read8(get_reg(ins.rs()) + offset);
    if(data_s & 0b10000000)
    {
        data_s |= 0xffffff00;
    }
 
    load_queue.push(RegisterLoad(ins.rt(), data_s, 1));
}
 
void CPU::BEQ()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    if(get_reg(ins.rs()) == get_reg(ins.rt()))
    {
        branch(offset);
    }
}
 
void CPU::BGTZ()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    if(int32_t(get_reg(ins.rs())) > 0)
    {
        branch(offset);
    }
}
 
void CPU::BLEZ()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    if(int32_t(get_reg(ins.rs())) <= 0)
    {
        branch(offset);
    }
}
 
void CPU::LBU()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
    {
        offset |= 0xffff0000;
    }
    uint32_t data = read8(get_reg(ins.rs()) + offset);
    load_queue.push(RegisterLoad(ins.rt(), data, 1));
}
 
void CPU::BLGE() //Choose between BLTZAL, BGEZAL, BLTZ, BGEZ
{
    //check if the 16th bit of the instruction is set
    if(ir & 0x00010000)
    {
        //check if the 20th bit of the instruction is set
        if(ir & 0x00100000)
            BGEZAL();
        else
            BGEZ();
    }
    else
    {
        //check if the 20th bit of the instruction is set
        if(ir & 0x00100000)
            BLTZAL();
        else
            BLTZ();
    }
}
 
void CPU::BLTZ()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
        offset |= 0xffff0000;
    int32_t op1 = get_reg(ins.rs());
    uint8_t val = op1 < 0;
    if(val)
        branch(offset);
}
 
void CPU::BLTZAL()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
        offset |= 0xffff0000;
    int32_t op1 = get_reg(ins.rs());
    uint8_t val = op1 < 0;
    if(val)
    {
        // uint32_t ra = pc + 4;
        uint32_t ra = pc;
        branch(offset);
        set_reg(31, ra);
    }
}
 
void CPU::BGEZ()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
        offset |= 0xffff0000;
    int32_t op1 = get_reg(ins.rs());
    uint8_t val = op1 >= 0;
    if(val)
        branch(offset);
}
 
void CPU::BGEZAL()
{
    uint32_t offset = ins.imm();
    //pad offset with bit at 16th position
    if(offset & 0x8000)
        offset |= 0xffff0000;
    int32_t op1 = get_reg(ins.rs());
    uint8_t val = op1 >= 0;
    if(val)
    {
        // uint32_t ra = pc + 4;
        uint32_t ra = pc;
        branch(offset);
        set_reg(31, ra);
    }
}
 
void CPU::SLTI()
{
    uint32_t imm_se = ins.imm();
    //pad offset with bit at 16th position
    if(imm_se & 0x8000)
        imm_se |= 0xffff0000;
    int32_t op1 = get_reg(ins.rs());
    int32_t op2 = imm_se;
    set_reg(ins.rt(), op1 < op2);
}
 
void CPU::SLTIU()
{
    uint32_t arg = ins.imm();
    //pad argument with bit at 16th position
    if(arg & 0x8000)
        arg |= 0xffff0000;
 
    uint32_t val = (get_reg(ins.rs()) < arg);
    set_reg(ins.rt(), val);
}